1. Field of the Invention
The present invention relates to a sense amplifier of a semiconductor memory device.
2. Description of the Related Art
A semiconductor memory device circuit such as a dynamic random access memory (DRAM) uses a sense amplifier to read data from a memory cell or to refresh data in the memory cell. FIG. 1 is a circuit diagram showing a conventional sense amplifier. In FIG. 1, the sense amplifier includes a pull-up sense amplifier 102 and a pull-down sense amplifier 104. The pull-up sense amplifier 102 includes PMOS transistors mp0 and mp1, and the pull-down sense amplifier 104 includes NMOS transistors mn0 and mn1. The MOS transistors mp1 and mp0 (and mn1 and mn0) are connected in series between a bit line BL and a complementary bit line BLB and have gates respectively coupled to the bit line BL and the complementary bit line BLB. The sense amplifier also includes a pull-up sense driver 106 and a pull-down driver 108 that provide and absorb electric charge from the lines BL and BLB via the pull-up sense amplifier 102 and the pull-down sense amplifier 104, respectively. In this sense amplifier, the pull-up sense driver 106 is a PMOS transistor connected between a supply voltage Vdd and a node between PMOS transistors mp0 and mp1, and the pull-down sense driver 108 is an NMOS transistor connected between ground and a node between NMOS transistors mn0 and mn1. The pull-up sense driver 106 and the pull-down sense driver 108 operate as a current source and a current sink, respectively.
FIG. 2 shows a control circuit for generating a signal LAPG and a signal LANG, which respectively operate the pull-up sense driver 106 and the pull-down sense driver 108 shown in FIG. 1. The control circuit of FIG. 2 includes a NAND gate 202 and three inverters 204, 206, and 208. When both input signals PS and PBLSIJ to the NAND gate 202 are in a "high" state, the output signal from the NAND gate 202 is in a "low" state. Accordingly, the signal LANG, which is the output of a first inverter 204, is in a "high" state, and the signal LAPG, which is the output of a third inverter 208, is in a "low" state. When signals PS and PBLSIJ are in the "high" state, the signal LANG turns on the pull-down sense driver 108, and the signal LAPG turns on the pull-up sense driver 106 for a sensing operation in the circuit of FIG. 1.
As illustrated in FIG. 1, the conventional sense amplifier uses a PMOS transistor as the pull-up sense driver 106 for providing electric charge to a line LA, and uses an NMOS transistor as the pull-down sense driver 108 for absorbing electric charge from a line LAB.
Sense amplifies such as in FIG. 1 must be adapted as the capacity of memory cell arrays increases. For example, conventional memory cell arrays were 128 Kbits in capacity, but are now increasing to 192 Kbits or 256 Kbits to decrease the chip size of semiconductor devices. As the capacities of memory arrays increase, bit lines are becoming thinner and longer, which increases the resistance and capacitance of the bit lines. The driving capability of the pull-up sense driver 106 and the pull-down sense driver 108 must correspondingly increase with the array capacity. Additionally, PMOS transistors respond to an activation signal more slowly than would an NMOS transistor of the same size. Accordingly, to equalize the response of the pull-up sense driver 106 (realized by a PMOS transistor) with that of the pull-down sense driver 108 (realized by the NMOS transistor), the width of the PMOS transistor needs to be larger than that of the NMOS transistor. However, the larger PMOS transistors (being present in all of the sense amplifiers of the memory) increase chip size and reduce the advantage obtained from a larger capacity memory cell array.